1. Field of the Invention
This invention generally relates to data processing systems and more specifically to apparatus for interconnecting the various units comprising the system.
2. Description of the Prior Art
A digital data processing system generally comprises three basic elements: a memory unit, an input/output element and a processor element. The memory element stores information in addressable storage locations. This information includes both data and instructions for processing the data. The processor element causes information to be transferred between it and the memory element, interprets the incoming information as either data or instructions and processes the data in accordance with the instructions. The input/output elements also communicate with the memory element in order to transfer input information to the system and to obtain processed information from it.
Over the years, as the demands for computing power and speed have increased, it has been suggested and is known to use several processor elements in a single processing system. In such multi-processing systems, it is normally desirable that each of the processors have partial or complete access to the same memory elements and input/output elements. It is therefore necessary to provide means to prevent the processors from accessing the same element simultaneously. Several arrangements for this are known. In a first arrangement, the processing elements are assigned priority levels whereby processing units having a higher priority are permitted to access the memory elements and input output elements over processing units having lower priority. This inevitably slows the turnaround for programs being run on the units having lesser priority.
A second arrangement is to provide a computer network including a master computer system to arbitrate between a plurality of slave processors. This arbitration may be determined by such factors as the length of time a slave processor would have to access the memory element or the input/output element, the length of time since its last access, or the like. However, if the master system malfunctions, the slaves are prevented from accessing the memory or input/output elements until the master system is repaired. Furthermore, the master system may create a bottleneck if the requests for access to the memory or input/output elements are too rapid for the master system to arbitrate, slowing the slave processors.
In a third arrangement an interaction control unit may be connected between the processing units and the memory units and input/output units to control access between the processing units and the memory units and the input/output units. The interaction control unit does not prevent the processing units themselves from operating while they are waiting to access the memory units and input/output elements. This arrangement otherwise has the same problems as the master-slave processing arrangement discussed above.
Furthermore, as the increase in demands for computing power have increased, more and more control information has to be passed among the various elements of the system. This has required addition of a number of control lines among the elements, adding to the expense both for the control lines themselves and for the additional electronic circuitry required to interpret information on the lines and place information on the lines.